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NX2715
SINGLE CHANNEL MOBILE PWM CONTROLLER WITH NMOS LDO CONTROLLER, PGOOD INDICATOR AND ENABLE
ADVANCE DATA SHEET Pb Free Product
DESCRIPTION
The NX2715 controller IC is a compact synchronous Buck controller IC with 16 lead MLPQ package designed for step down DC to DC converter applications with feedforward functionality. Voltage feedforward provides fast response, good line regulation and nearly constant power stage gain under wide voltage input range. The NX2715 controller is optimized to convert single supply up to 24V bus voltage to as low as 0.8V output voltage. Internal UVLO keeps the controller off until the bus supply voltage exceeds 7V where internal digital soft starts get initiated to ramp up output. The NX2715 employs NMOS LDO controller, programmable current limiting and FB UVLO followed by latchout feature. Other features include: 5V gate drive, programmable frequency, over voltage protection, adaptive deadband control and Vcc under voltage lockout.
n n n n n n n n n n n n n n n
FEATURES
Bus voltage operation from 7V to 24V Less than 1uA shutdown current with Enable low Excellent dynamic response with input voltage feed-forward and voltage mode control Programmable switching frequency Internal digital soft start function Programmable current limit triggers latch out FB UVLO followed by latch out feature NMOS LDO controller available Power Good indicator available Start into precharged output Pb-free and RoHS compliant
APPLICATIONS
Notebook PC Graphic Card on board converters On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V Set Top Box and LCD Display
TYPICAL APPLICATION
MBR0530T1 8 VIN BST 16 0.1uF HDRV 1 Q1 1.5uH
VIN1 +7V to 20V
33uF(25V POSCAP)
1uF
VIN3 +5V
10
13 1uF
PVCC
SW 15 OCP 10
6k 3.9nF Q2 1k 2.49k 18nF 12.4k 1nF 6.98k
VOUT1 +1.25V@10A
2*2R5TPE330MC
14 1uF
VCC
NX2715
LDRV 3 PGND 2 FB COMP 11 12
9
EN
4 RT 100k 5 PGOOD AGND LDO OUT 6 2.7nF 2.7k 4.22k 1k 22uF ceramic MTD3055
(PAD)
LDO FB 7
VOUT2 +1V@2A
Figure1 - Typical application of NX2715
ORDERING INFORMATION
Device NX2715CMTR
Rev. 1.4 01/08/08
Temperature 0 to 70o C
Package MLPQ -16L
Frequency 200kHz to 1MHz
Pb-Free Yes 1
NX2715
ABSOLUTE MAXIMUM RATINGS
VCC to GND & BST to SW voltage ...................... -0.3V to 6.5V VIN to GND ........................................................ -0.3V to 25V BST to GND Voltage ......................................... -0.3V to 35V SW to GND ....................................................... -2V to 35V All other pins ..................................................... -0.3V to 6.5V Storage Temperature Range ................................ -65oC to 150oC Operating Junction Temperature Range ................ -40oC to 125oC ESD Susceptibility ............................................ 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
PACKAGE INFORMATION
16-LEAD PLASTIC MLPQ
PVCC
VCC
BST
JA 46o C/W
SW
16 HDRV 1 PGND 2 LDRV 3 RT 4 5 PGOOD
15
14
13 12 COMP
17 AGND
11 FB 10 OCP 9 EN
6 LDO-OUT
7 LDO-FB
8 VIN
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc =5V, VIN=15V and TA = 0 to 70oC. Typical values refer to TA = 25oC.
PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range Operating quiescent current Shut down current Vcc UVLO VCC-Threshold VCC-Hysteresis SYM VREF Test Condition Min TYP 0.8 0.2 4.75 EN=HIGH EN=LOW 3 5.25 5 1 MAX Units V % V mA uA V V
VCC IQ ISD
VCC_UVLO VCC Rising VCC_Hyst VCC Falling
4.4 0.2
Rev. 1.4 01/08/08
2
NX2715
PARAMETER Supply Voltage(Vin) Vin Voltage Range Input Voltage Current Shut Down Current Vin UVLO Vin-Threshold Vin-Hysteresis Oscillator (Rt) Frequency Frequency Over Vin Ramp-Amplitude Voltage Ramp Offset Ramp/Vin Gain Max Duty Cycle Min on time Error Amplifiers Transconductance Input Bias Current Comp SD threshold Vref and Soft Start Soft Start time High Side Driver(CL=3300pF) Sourcing Output Impedance , Current Output Impedance , Sinking Current Rise Time Fall Time N Deadband Time Low Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time OCP Adjust OCP current setting Enable Enable HI Threshold Enable LOW Threshold
Rev. 1.4 01/08/08
SYM Vin
Test Condition
Min 7
TYP
MAX 25 40 1
Units V uA uA V V KHz % V V V/V % nS umho nA V mS ohm ohm ns ns ns
Vin=24V EN=LOW Vin_UVLO Vin_Hyst FS VRAMP Vin Rising Vin Falling RT=open -5 Vin=20V
24
6 0.5 200 5 2 0.8 0.1 88 150 2500
Ib 0.3 Tss Rsource(Hdrv) Rsink(Hdrv) RT=open I=200mA I=200mA 10 1 0.8 50 50 30
100
THdrv(Rise) 10% to 90% THdrv(Fall) 90% to 10% Tdead(L to Ldrv going Low to Hdrv going H) High, 10% to 10% Rsource(Ldrv) Rsink(Ldrv) I=200mA I=200mA
1 0.5 50 50 30
ohm ohm ns ns ns
TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10%
32 1.4 0.4
uA V V 3
NX2715
PARAMETER Power Good(Pgood) Threshold Voltage as % of Vref Hysteresis FBUVLO Feedback UVLO threshold Over temperature Threshold Hysteresis LDO Controller FB Pin- Bias Current LDO FB Voltage LDO FB UVLO High Output Voltage Low Output Voltage High Output Source Current Over Voltage Protection Threshold Voltage as % of Vref Hysteresis SYM Test Condition FB ramping up Min TYP 90 5 percent of nominal 65 70 150 20 100 percent of nominal VIN=12V 65 0.8 70 10.2 0.2 3 130 45 75 75 MAX Units % % %
o o
C C
nA V % V V mA % %
FB ramping up
Rev. 1.4 01/08/08
4
NX2715
PIN DESCRIPTIONS
PIN SYMBOL VCC PIN DESCRIPTION This pin supplies the internal 5V bias circuit. . A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. This pin supplies voltage to high side FET driver. A high freq minimum 0.1uF ceramic capacitor is placed as close as possible to and connected to this pin and SW pin. Analog ground. This pin is the error amplifiers inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is connected to source of high side FETs and provide return path for the high side driver. High side gate driver output. Low side gate driver output. Bus voltage input provides power supply to oscillator and VIN UVLO signal. Pull up this pin to Vcc for normal operation. Pulling this pin down below 0.4V shuts down the controller and resets the soft start. LDO FB LDO controller feedback input. If the LDOFB pin is pulled below 0.7*Vref, an internal comparator after certain delay and pulls down LDOOUT pin and initiates the HICCUP circuitry. LDO controller output. This pin is controlling the gate of an external NCH MOSFET. The maximum rating of this pin is 16V. An open drain output that requires a pull up resistor to Vcc or a voltage lower than Vcc. When FB pin reaches 90% of the reference voltage PGOOD transitions from LO to HI state. This pin is connected to the drain of the external low side MOSFET and is the input of the over current protection(OCP) comparator. An internal current source is flown to the external resistor which sets the OCP voltage across the Rdson of the low side MOSFET. Current limit point is this voltage divided by the Rds-on. Power ground. Ldrv supply voltage. A 1uF high frequency cap must be connected from this pin to GND directly. RT
Rev. 1.4 01/08/08
BST AGND
FB
COMP
SW HDRV LDRV VIN
EN
LDO OUT
PGOOD
OCP
PGND PVCC
Oscillator's frequency can be set by using an external resistor from this pin to GND. When RT pin is open, the frequency is 200kHz. 5
NX2715
BLOCK DIAGRAM
FB 0.85Vref /0.90Vref PGOOD
VCC
4.4/4.2 Bias 1.25V Generator 0.8V 6/5.75 COMP 0.3V
EN
POR BST START Hiccup Reset dominant START DrvH
VIN
DISABLE RT START Digital start Up VIN SS_1/4_done OSC Dis_EA SS_half_done S R Vp Vp Q FB 1.30Vref /0.85Vref OVP FET Drivers PWM
SW
PVCC DRVL
PGND SS_half_done 70%*Vp FB
POR latch R Latchout logic 0.6V CLAMP 32uA START VCC
FB
OCP
COMP Dis_EA AGND EN
0.6V 70%*Vp SS_1/4_done
EN
DISABLE Vp
VpLDO
LDO OUT
LDO FB
Figure 2 - Simplified block diagram of the NX2715
Rev. 1.4 01/08/08
6
NX2715
MBR0530T1 8 VIN BST 16 0.1uF HDRV 1 Q1 FDS8878 1.5uH 6k 3.9nF Q2 FDS6676AS 1k 2.49k 18nF
VIN1 +7V to 20V
33uF(25V POSCAP)
1uF
VIN3 +5V
10
13 1uF
PVCC
SW 15 OCP 10
VOUT1 +1.25V@10A
2*2R5TPE330MC 6.98k
NX2715
LDRV 3 PGND 2 11 FB 12 COMP
14 1uF
VCC
12.4k 1nF
9
EN
4 RT 100k 5 PGOOD AGND LDO OUT 6 2.7nF 2.7k 4.22k 1k 22uF ceramic MTD3055
(PAD)
LDO FB 7
VOUT2 +1V@2A
Figure 3 - Simplified Demo board schematic
Rev. 1.4 01/08/08
7
NX2715
5V
1
5V
L1 VDD C1 1u 14 R1 10 13 C5 1u D1 MBR0530T1 BST 8 7 6 5 9 16 C8 0.1u 4 M3B open 3 C7 0.1u SHORT C9 25TQC33M C12 open 1 GNDIN VIN 1 VIN
U1 VIN C11 1u 8 VIN
VCC
PVCC
HDRV R14 5V 100k
1
R5 0
M1 4
F D S 8878
5 6
SW 1
JVOUT
1 2 3
C2 0.1u 15
C15 0.1u 1.25V
SW R15 VIN 100k OUT R16 open
L2 SW OUT DO5010P-152HC C13 C14 R8 1k GNDOUT VOUT 10 R2 6k C19 open
EN
NX2715
9
OCSET
C20 10u (cer) M4 MTD3055 JLDO_OUT 1 2 3 4 5 C6 2.7n 1V R4 2.7k R13 1k GNDLDO 1 C18 22u (cer) R12 4.22k 7 R17 0 6 LDO_OUT
8 7 6 5 9
LDRV
3
R6 0
M2 4
FDS6676AS
2R5TPE330MC 2R5TPE330MC
7 8
C10 470p M3A open R7 10
C16 3.9n R10 6.98k R9 1k
1 2 3
2 2
C17 0.1u LDO_OUT 1
PGND
LDO_FB FB
11 C4 18n C3 1n R3 2.49 R11 12.4k
R18 5V open
4 R19 open
RT PAD
COMP
12
Figure 4 - Demo board schematic based on ORCAD
Rev. 1.4 01/08/08
17
1
5 4 3 2
5
PGOOD
8
NX2715
Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Quantity 3 5 1 1 1 1 1 2 1 1 1 1 1 1 1 1 2 1 1 1 3 3 1 1 1 2 1 Reference C1,C5,C11 C2,C7,C8,C15,C17 C3 C4 C6 C9 C10 C13,C14 C16 C18 C20 D1 L2 M1 M2 M4 R1,R7 R2 R3 R4 R5,R6,R17 R8,R9,R13 R10 R11 R12 R14,R15 U1 Part 1u 0.1u 1n 18n 2.7n 25TQC33M 470p 2R5TPE330MC 3.9n 22u 10u MBR0530T1 DO5010P-152HC FDS8878 FDS6676AS MTD3055 10 6k 2.49 2.7k 0 1k 6.98k 12.4k 4.22k 100k NX2715
Rev. 1.4 01/08/08
9
NX2715
Demoboard waveforms
Fig.5 Startup
Fig.6 Startup with preload
Fig.7 Voltage Ripple of 1.25V output
Fig.8 Output short into latch out
Fig. 9 Dynamic response of 1.25V output
Rev. 1.4 01/08/08
Fig. 10 Dynamic response of LDO output 10
NX2715
APPLICATION INFORMATION
Symbol Used In Application Information:
VIN VOUT IOUT FS DIRIPPLE - Input voltage - Output voltage - Output current - Switching frequency - Inductor current ripple
IRIPPLE = =
VIN -VOUT VOUT 1 x x LOUT VIN FS
...(2) 20V-1.25V 1.25V 1 x x = 3.9A 1.5uH 20V 200kHz
Output Capacitor Selection
Output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load condition is determined by equation(3).
DVRIPPLE - Output voltage ripple
Design Example
Power stage design requirements: VIN=7-20V VOUT=1.25V IOUT =10A DVRIPPLE <=25mV DVTRAN<=60mV @ 5A step FS=200kHz
VRIPPLE = ESR x IRIPPLE +
IRIPPLE 8 x FS x COUT
...(3)
Where ESR is the output capacitors' equivalent series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected such as Aluminum Electrolytic,POSCAP and OSCON types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. For this example, POSCAP are chosen as output capacitors, the ESR and inductor current typically determines the output voltage ripple.
Output Inductor Selection
The selection of inductor value is based on inductor ripple current, power rating, working frequency and efficiency. Larger inductor value normally means smaller ripple current. However if the inductance is chosen too large, it brings slow response and lower efficiency. Usually the ripple current ranges from 20% to 40% of the output current. This is a design freedom which can be decided by design engineer according to various application requirements. The inductor value can be calculated by using the following equations:
ESR desire =
VRIPPLE 25mV = = 6.4m IRIPPLE 3.9A
...(4)
If low ESR is required, for most applications, multiple capacitors in parallel are better than a big capacitor. For example, for 25mV output ripple, POSCAP 2R5TPE330MCC2 with 12m are chosen.
V -V V 1 L OUT = IN OUT x OUT x IRIPPLE VIN FS IRIPPLE =k x IOUTPUT
where k is between 0.2 to 0.4. Select k=0.3, then
...(1)
N=
E S R E x IR I P P L E VR IPPLE
...(5)
20V-1.25V 1.25V 1 x x 0.4 x10A 20V 200kHz LOUT =1.5uH LOUT =
Choose LOUT=1.5uH, then coilcraft inductor DO5010P-152HC is a good choice. Current Ripple is calculated as
Rev. 1.4 01/08/08
Number of Capacitor is calculated as
N= 12m x 3.9A 25mV
N =1.9 The number of capacitor has to be round up to a integer. Choose N =2. 11
NX2715
If ceramic capacitors are chosen as output capacitors, both terms in equation (3) need to be evaluated to determine the overall ripple. Usually when this type of capacitors are selected, the amount of capacitance per single unit is not sufficient to meet the transient specification, which results in parallel configuration of multiple capacitors. capacitor output ripple is : The amount of ceramic output inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the ESR of output capacitor. For low frequency capacitor such as electrolytic capacitor, the product of ESR and capacitance is high and L L crit is true. In that case, the transient spec is mostly like to dependent on the ESR of capacitor. Most case, the output capacitor is multiple capacitor in parallel. The number of capacitor can be calculated by the following
N= ESR E x Istep Vtran + VOUT x 2 2 x L x C E x Vtran
VRIPPLE = ESR x IRIPPLE
IRIPPLE + 8 x 200kHz x COUT
Using the above equations, although DC ripple spec can be met, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient is specified as V droop < V tran @step load DISTEP During the transient, the voltage droop during the transient is composed of two sections. One section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, for the overshoot when load from high load to light load with a DISTEP transient load, if assuming the bandwidth of system is high enough, the overshoot can be estimated as the following equation.
...(9)
where
0 if L L crit = L x Istep - ESR E x CE V OUT
sient is 60mV for 5A load step. If the POSCAP
if
L L crit
...(10)
For example, assume voltage droop during tran2R5TPE330MCC2(330uF,
12mohm ESR) is used, the crticial inductance is given as
Lcrit =
ESR E x CE x VOUT = Istep
12mx 330F x1.25V = 0.99H 5A
The selected inductor is 1.5uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is
Vovershoot
where
VOUT = ESR x Istep + x 2 2 x L x COUT
...(6)
is the a function of capacitor,etc.
L L crit
...(7)
0 if L L crit = L x Istep - ESR x COUT V OUT
where
L crit =
if
= =
L x Istep VOUT
- ESR E x C E
1.5H x 5A - 12m x 330F = 2.04us 1.25V
ESR E x Istep Vtran + VOUT x 2 2 x L x CE x Vtran
ESR x COUT x VOUT ESR E x C E x VOUT = ...(8) Istep I step
N= =
where ESRE and CE represents ESR and capacitance of each capacitor if multiple capacitors are used in parallel. The above equation shows that if the selected
12m x 5A + 60mV 1.25V x 2.04us2 2 x1.5H x 330F x 60mV = 1.74
12
Rev. 1.4 01/08/08
NX2715
The number of capacitors has to satisfy both ripple and transient requirement. Overall, we choose N=2. It should be considered that the proposed equation is based on ideal case, in reality, the droop or overshoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. pensate the system with type III compensator. The following figures and equations show how to realize the type III compensator by transconductance amplifier.
FZ1 = FZ2 = FP1 = FP2 =
1 2 x x R 4 x C2 1 2 x x (R 2 + R3 ) x C3 1 2 x x R3 x C3 1 C x C2 2 x x R4 x 1 C1 + C2
...(11) ...(12) ...(13) ...(14)
Compensator Design
Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. Ideally, the Bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, because the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. Voltage feedforward is used in NX2715 to compensate the output voltage variation caused by input voltage changing. The feedforward funtion is realized by using VIN pin voltage to program the oscillator ramp voltage VOSC at about 1/10 of VIN voltage, which provides nearly constant power stage gain under wide voltage input range.
where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. The transfer function of type III compensator for transconductance amplifier is given by:
Ve 1 - gm x Z f = VOUT 1 + gm x Zin + Z in / R1
For the voltage amplifier, the transfer function of compensator is
Ve -Z f = VOUT Zin
To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R4>>2/gm. And it would be desirable if R1||R2||R3>>1/gm can be met at the same time.
Zin R3
Vout
Zf C1 C2 Fb gm Ve R4
R2 C3 R1
Vref
A. Type III compensator design
For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to comRev. 1.4 01/08/08
Figure 11 - Type III compensator using transconductance amplifier
13
NX2715
Case 1: FLCGain(db)
power stage
C2 = =
40dB/decade
1 2 x x FZ1 x R 4
FLC
1 2 x x 0.75 x 5.06kHz x 2.5k = 17nF
Choose C2=18nF.
loop gain
4. Calculate C1 by equation (14) with pole Fp2 at
FESR
20dB/decade compensator
one third of the switching frequency.
C1 = =
1 2 x x R 4 x FP2
1 2 x x 2.5k x 66.7kHz = 959pF
Choose C1=1nF.
FZ1 FZ2
FO FP1
FP2
5. Calculate C3 with the crossover frequency FO at 15kHz.
Figure 12 - Bode plot of Type III compensator (FLCC3 = =
VOSC 2 x x FO x L x COUT x VIN R4
1 2 x x 15kHz x 1.5uH x 660uF x 10 2.5k =3.7nF
Choose C3=3.9nF. 6. Calculate R3 by equation (13) with Fp1 =FESR.
R3 = =
1 2 x x FP1 x C3
1 2 x x 40kHz x 3.9nF = 1k
Choose R3 =1k. 7. Calculate R2 by setting compensator zero FZ2 at the LC double pole.
FLC = =
1 2 x x L OUT x COUT 1
2 x x 1.5uH x 660uF = 5.06kHz
R2 = =
1 1 1 x( - ) 2 x x C3 FZ2 FP1
FESR = =
1 2 x x ESR x C OUT
1 2 x x 6m x 660uF = 40kHz
Rev. 1.4 01/08/08
1 1 1 x( - ) 2 x x 3.9nF 5.06kHz 40kHz = 7.05k
Choose R2 =6.98k. 14
NX2715
8. Calculate R1
.
FESR = =
R x VREF 6.98k x 0.8V R1 = 2 = = 12.41k VOUT -VREF 1.25V-0.8V
Choose R1=12.4k. Case 2: FLC1 2 x x ESR x COUT
1 2 x x 9m x 2000uF = 8.8kHz
2. Set R4 equal to 2.5k. 3. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11).
Gain(db)
power stage
FLC
40dB/decade
C2 = =
1 2 x x FZ1 x R 4
FESR
loop gain
1 2 x x 0.75 x 2.4kHz x 2.5k = 35nF
Choose C2=33nF. 4. Calculate C1 by equation (14) with pole Fp2 at one third of the switching frequency.
20dB/decade
C1
compensator
1 2 x x R 4 x FP2
1 2 x x 2.5k x 66.7kHz 959pF
FZ1 FZ2 FP1 FO
FP2
Choose C1=1nF. 5. Calculate R3 with the crossover frequency FO at 15kHz.
Figure 13 - Bode plot of Type III compensator (FLCVIN ESR x R 4 x VOSC 2 x x FO x L
=10 x
9mohm x 2.5k 2 x x 15kHz x 1uH =1.08k
Choose R3=1.2k. 6. Calculate C3 by equation (13) with Fp1 =FESR.
C3 = =
1 2 x x FP1 x R3
FLC = =
1 2 x x LOUT x COUT 1
1 2 x x 8.8kHz x 1.2k = 14nF
Choose C3 =15nF. 7. Calculate R2 by setting compensator zero FZ2 at the LC double pole.
2 x x 2.2uH x 2000uF = 2.4kHz
Rev. 1.4 01/08/08
15
NX2715
R2 = = 1 1 1 x( - ) 2 x x C3 FZ2 FP1
The following equations show the compensator pole zero location and constant gain.
1 1 1 x( - ) 2 x x 15nF 2.4kHz 8.8kHz = 3.2k
Choose R2 =4k. 8. Calculate R1
Gain=gm x Fz =
R1 x R3 R1 +R 2
...(15) ... (16) ... (17)
1 2 x x R3 x C1 1 2 x x R 3 x C2
.
R x VREF 4k x 0.8V R1 = 2 = = 12.8k VOUT -VREF 1.05V-0.8V
Choose R1=12.7k.
Fp
Vout R2 Fb gm R1 Vref Ve R3 C2 C1
B. Type II compensator design
If the electrolytic capacitors are chosen as power stage output capacitors, usually the Type II compensator can be used to compensate the system. For this type of compensator, FO has to satisfy FLCpower stage Gain(db) 40dB/decade loop gain 20dB/decade
Figure 15 - Type II compensator with transconductance amplifier The following is parameters for type II compensator design. Input voltage is 12V, output voltage is 2.5V, output inductor is 2.2uH, output capacitors are two 680uF with 41m electrolytic capacitors. 1.Calculate the location of LC double pole FLC and ESR zero FESR.
compensator Gain
FLC = =
1 2 x x L OUT x COUT 1
FZ FLC FESR
FO FP
2 x x 2.2uH x 1360uF = 2.9kHz
Figure 14 - Bode plot of Type II compensator Type II compensator can also be realized by simple RC circuit without feedback as shown in figure 15. R3 and C1 introduce a zero to cancel the double pole effect. C2 introduces a pole to suppress the switching noise.
Rev. 1.4 01/08/08
FESR = =
1 2 x x ESR x COUT
1 2 x x 20.5m x 1360uF = 5.7kHz
16
NX2715
1.Set R2 equal to10k. Using equation 18, the final selection of R1 is 4.7k. 2. Set crossover frequency at 1/20 of the swithing frequency, here FO=10kHz. 3.Calculate R3 value by the following equation.
Vout R2 Fb R1 Vref
V 2 x x FO x L 1 VOUT x x R3 = OSC x Vin RESR gm VREF 1 2 x x 10kHz x 2.2uH 1 x x 10 20.5m 2.5mA/V 2.5V x 0.8V =0.8k =
Choose R3 =1k. 4. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole.
Figure 16 - Voltage divider
R 1=
R 2 x VR E F V O U T -V R E F
...(18)
where R2 is part of the compensator, and the value of R1 value can be set by voltage divider.
Input Capacitor Selection
Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk capacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are decided by voltage rating and RMS current rating. The RMS current in the input capacitors can be calculated as:
C1 = =
1 2 x x R 3 x Fz
1 2 x x 1k x 0.75 x 2.9kHz =70nF
Choose C1=68nF. 5. Calculate C2 by setting compensator pole Fp at half the swithing frequency.
C = 1 xR
3
2
x Fs
1 = x 1k x 3 0 0 k H z =530pF
IRMS = IOUT x D x 1- D D= VOUT VINMIN
...(19)
Choose C2=560pF.
VINMIN = 7V, VOUT=1.05V, IOUT=10A, the result of input RMS current is 3.8A. For higher efficiency, low ESR capacitors are recommended. One Sanyo OSCON CAP 25SVP56M 25V 56uF 28m with 3.8A RMS rating are chosen as input bulk capacitors.
Output Voltage Calculation
Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors so that the output voltage applied at the Fb pin is 0.8V when the output voltage is at the desired value. The following equation applies to figure 16, which shows the relationship between vider.
VOUT , VREF and voltage di-
Rev. 1.4 01/08/08
17
NX2715
Power MOSFETs Selection
The NX2715 requires two N-Channel power MOSFETs. The selection of MOSFETs is based on maximum drain source voltage, gate source voltage, maximum current rating, MOSFET on resistance and power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter efficiency. For example, two IRF7822 are used in application. They have the following parameters: VDS=30V, ID =18A,RDSON =6.5m,QGATE =44nC. There are two factors causing the MOSFET power loss:conduction loss, switching loss. Conduction loss is simply defined as: This power dissipation should not exceed maximum power dissipation of the driver device.
Over Current Limit Protection
Over current protection is achieved by sensing current through the low side MOSFET. An internal current source of 32uA flows through an external resistor connected from OCP pin to SW node sets the over current protection threshold. When synchronous FET is on, the voltage at node SW is given as
VSW =-IL x RDSON
The voltage at pin OCP is given as
IOCP x ROCP +VSW
When OCP pin voltage is below zero, the over ...(20) current occurs after three cycles as shown in figure 17, both Hdrv and Ldrv will be shut down.
PHCON =IOUT x D x RDS(ON) x K
2
PLCON =IOUT 2 x (1 - D) x RDS(ON) x K PTOTAL =PHCON + PLCON
where the RDS(ON) will increases as MOSFET junction temperature increases, K is RDS(ON) temperature dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125oC according to datasheet. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated.
1 x VIN x IOUT x TSW x FS ...(21) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Swithing loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: PSW =
Pgate = (QHGATE x VHGS + QLGATE x VLGS ) x FS
vbus I OCP 32uA
OCP R OCP
SW
...(22)
OCP comparator
where QHGATE is the high side MOSFETs gate charge,QLGATE is the low side MOSFETs gate charge,VHGS is the high side gate source voltage, and VLGS is the low side gate source voltage.
Rev. 1.4 01/08/08
Figure 17 - Over Current Protection Waveform and Block Diagram
18
NX2715
The over current limit can be set by the following equation: where FO is the desired crossover frequency. Typically, in this LDO compensation, crossover frequency FO has to be higher than zero caused by ESR. FO is typically around several tens kHz to a few hundred kHz. For this example, we select Fo=100kHz. gm is the forward trans-conductance of MOSFET.
LDO input Vref Rf1 Rf2 Rc Cc Co ESR
+
ISET =
IOCP x ROCP K x RDSON
If MOSFET RDSON=6.5m, the worst case thermal consideration K=1.5 and the current limit is set at 15A, then
R OCP = ISET x K x RDSON 15A x 1.5 x 6.5m = = 4.57k IOCP 32uA
Choose ROCP=4.64k. For NX2715, if switching channel goes into OCP and latch up, the LDO will be latch up at the same time.
Rload
LDO Selection Guide
NX2715 offers a LDO controller. The selection of MOSFET to meet LDO is more straight forward. The selection is that the Rdson of MOSFET should meet the dropout requirement. For example. VLDOIN =3.3V VLDOOUT =2.5V ILoad =2A The maximum Rdson of MOSFET should be
R RDSON = (VLDOIN - VLDOOUT ) x I LOAD = (3.3V - 2.5V) / 2A = 0.4
Figure 18 - NX2715 LDO controller. For IRFR3706, gm=53. Select Rf1=5kohm. Output capacitor is Sanyo POSCAP 4TPE150MI with 150uF, ESR=18mohm. CC = 1 53 x 18m x =77pF 4 x x 100kHz x 5k 1+53 x 18m
Most of MOSFETs can meet the requirement. More important is that MOSFET has to be selected right package to handle the thermal capability. For LDO, maximum power dissipation is given as
PLOSS = (VLDOIN - VLDOOUT ) x I LOAD = (3.3V - 2.5V) x 2A = 1.6W
Choose CC=82pF. For electrolytic or POSCAP, RC is typically selected to be zero. Rf2 is determined by the desired output voltage.
R f2 = =
R f1 x VREF VLDOOUT - VREF
Select IR MOSFET IRFR3706 with 9m RDSON is sufficient.
5k x 0.8V 1.6V - 0.8V =5k
Choose Rf2=5k. When ceramic capacitors or some low ESR bulk capacitors are chosen as LDO output capacitors, the zero caused by output capacitor ESR is so high that crossover frequency FO has to be chosen much higher than zero caused by RC and CC and much lower than zero caused by ESR . For example, 22uF ceramic is used as output capacitor. We select Fo=100kHz, Rf1=1kohm and select MOSFET MTD3055(gm=5). R C and CC can be calculated as follows. 19
LDO Compensation
The diagram of LDO controller including VCC regulator is shown in the following figure. For most low frequency capacitor such as electrolytic, POSCAP, OSCON, etc, the compensation parameter can be calculated as follows.
CC =
g x ESR 1 xm 4 x x FO x R f1 1+gm x ESR
Rev. 1.4 01/08/08
NX2715
RC =R f1 x 2 x x FO x CO 0.5 x gm 2 x x 100kHz x 22uF 0.5 x 5S
Layout Considerations
The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. There are two sets of components considered in the layout which are power components and small signal components. Power components usually consist of input capacitors, high-side MOSFET, low-side MOSFET, inductor and output capacitors. A noisy environment is generated by the power components due to the switching power. Small signal components are connected to sensitive pins or nodes. A multilayer layout which includes power plane, ground plane and signal plane is recommended . Layout guidelines: 1. First put all the power components in the top layer connected by wide, copper filled areas. The input capacitor, inductor, output capacitor and the MOSFETs should be close to each other as possible. This helps to reduce the EMI radiated by the power loop due to the high switching currents through them. voltage exceeds 2. Low ESR capacitor which can handle input RMS ripple current and a high frequency decoupling
=1k x =5.4k
Choose RC=5.4k. 10 x CO CC = RC x gm 10 x 22uF = 2 x x 5.4k x 5S =1.3nF Choose CC=1.2nF.
Current Limit for LDO
Current limit of LDO is achieved by sensing the LDO feedback voltage. When LDO_FB pin is below 70% of VREF, the IC goes into latch up. The IC will turn off all the channel and latch up.
Over Voltage Protection
When FB pin 1.04V(130%*VRE F) and be there for three cycles, over voltage protection will be triggered. Hdrv turns low and Ldrv turns high. Ldrv will be from high to low once FB voltage falls below 0.68V(85%*V REF ).
need to be practically touching the drain pin of the upper MOSFET, a
ceramic cap which usually is 1uF plane connection is a must. 3. The output capacitors should be placed as close as to the load as possible and plane connection is required. 4. Drain of the low-side MOSFET and source of the high-side MOSFET need to be connected thru a plane ans as close as possible. A snubber nedds to be placed as close to this junction as possible. 5. Source of the lower MOSFET needs to be connected to the GND plane with multiple vias. One is not enough. This is very important. The same applies to the output capacitors and input capacitors. 6. Hdrv and Ldrv pins should be as close to MOSFET gate as possible. The gate traces should be wide and short. A place for gate drv resistors is needed to fine tune noise if needed.
Figure 19 - OVP trigger threshold.
Rev. 1.4 01/08/08
7. Vcc capacitor, BST capacitor or any other by20
NX2715
passing capacitor needs to be placed first around the IC and as close as possible. The capacitor on comp to GND or comp back to FB needs to be place as close to the pin as well as resistor divider. 8. The output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. All GNDs need to go directly thru via to GND plane. 10. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. 11. In multilayer PCB, separate power ground and analog ground. These two grounds must be connected together on the PC board layout at a single point. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function.
Rev. 1.4 01/08/08
21

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